Currently, semiconductor memory devices provide various operational modes with wide applications. For example, synchronous semiconductor memory devices (such as a SDRAM (synchronous dynamic random access memory)) can support variable column address strobe latency (CL) and burst length (BL) modes using a mode register set (MRS). These semiconductor memory devices are used in various devices and applications such as electronic equipment, network systems, communication systems, control systems, multimedia applications, and main memories of PCs (personal computers).
FIGS. 1A through 1C illustrate a hierarchical memory architecture of a semiconductor memory device according to the prior art. As shown in FIG. 1A, a semiconductor memory device (100) includes a plurality of memory banks (100A, 100B, 100C, 100D). Each memory bank represents, for example, a logical unit of memory in a PC, and each bank may consist of one or more memory modules (e.g., DIMM (Dual Inline Memory Module), SIMM (Single In-Line Memory Module)). Each memory bank (100A, 100B, 100C, 100D) is further logically divided into a plurality of memory cell array blocks. For instance, as depicted in the exemplary embodiment of FIG. 1B, the memory bank (100A) comprises four memory cell array blocks (100a, 100b, 100c, 100d).
In addition, each memory cell array block (100a, 100b, 100c, 100d) is further logically divided into a plurality of sub-memory cell array blocks, wherein each sub-memory array block is controlled by associated control circuitry. For instance, as depicted in the exemplary embodiment of FIG. 1C, the memory cell array block (100a) comprises four sub-memory cell array blocks (110, 120, 130, 140). The memory cell array block (100a) further comprises a plurality of word line drivers (111, 121, 131, 141), wherein each word line driver is associated with one of the sub-memory cell array blocks (110, 120, 130, 140), as well as a plurality of sub-decoders (112, 122, 132, 142) and a row decoder (150).
The memory framework depicted in FIGS. 1A-C is typically implemented in a partial activation semiconductor memory device, for example a fast cycle dynamic random access memory (FCRAM), whereby one of the sub-memory cell array blocks (110, 120, 130, 140) can be activated using, for example, column block addresses (CBAs) to perform data access or refresh operations.
By way of example, to perform a memory access operation, one of the memory banks (100A, 100B, 100C, 100D) is initially selected in response to a predetermined bank address, and then a memory cell array block (100a, 100b, 100c, 100d) within the selected memory bank is selected in response to a predetermined address (e.g., row address). Then, one sub-memory cell array block (in the selected memory cell array block) is selected in response to, e.g., a column block address (CBA). For instance, in the exemplary embodiment of FIG. 1C, since the memory cell array block (100a) comprises four sub-memory blocks (110, 120, 130, 140), two column block addresses (CBAs) are used to select one of the sub-memory blocks.
More specifically, during a write or read operation (memory access), a row address RAi (i=2, 3, . . . ,n) is input to the row decoder (150) and decoded. Then, based on the result of the decoding, the row decoder (150) will activate one of a plurality of normal word line enable signals (NWE) corresponding to the input row address RAi. In response to another row address RAi (i=0,1) and CBAs, one of the sub-decoders (112, 122, 132, 142) will generate a word line power supply signal having a predetermined boosting level, and output the word line power supply signal to a corresponding one of the wordline drivers (111, 121, 131, 141). In response to the wordline power supply signal and the wordline enable signal NEW, the wordline activates a corresponding one of the word lines (WL_0, WL_1, WL_2, WL_3) through a predetermined switching circuit (not shown). Once the word line is activated for the selected sub-memory cell array block, a column address is input and decoded to read or write data to the selected sub-memory block.
In a DRAM having the memory framework as depicted in FIGS. 1A-1C, since only one of the sub-memory cell array blocks (110, 120, 140, 140) can be activated at any given time, the page length of the semiconductor device is fixed. As is known in the art, a “page” refers to the number of bits that can be accessed from one row address, and the number of column addresses determines the size of the “page”. For instance, in the memory cell array block (100a) of FIG. 1C, assuming the total number of external input addresses is n, the total number of column addresses used to select a column select line (CSL) of each sub-memory cell array block is n−2. This is because two column addresses are used to select one of the four sub-memory cell array blocks (100a, 100b, 100c, 100d). Thus, a page length corresponding to an activated word line of a selected sub-memory cell array block is fixed at 2n−2. Accordingly, a conventional semiconductor memory device having a framework such as shown in FIG. 1C that provides a fixed page length of 2n−2 is not compatible with a semiconductor memory device (for example, SDRAM) having page length of 2n or 2n−1, for example.
Thus, a semiconductor memory device having an architecture that would enable the page length to be adjusted for a given application would be highly advantageous.